1. Technical Field
Exemplary embodiments relate to an etching composition for an under-bump metallurgy (UBM) layer, and a method of forming a bump structure. More particularly, exemplary embodiments relate to an etching composition for preventing and/or reducing impurities from being generated on a conductive bump, and a method of forming a bump structure using the same.
2. Description of the Related Art
Generally, a conductive bump is employed for electrically connecting a semiconductor chip with electronic equipment. An electrical die sorting (EDS) process may be performed to examine the performance of the semiconductor chip on which the conductive bump is formed. EDS processes measure electrical characteristics of the semiconductor chip on which the conductive bump is formed using a probe station to confirm whether the semiconductor chip has defects. The probe station includes a probe card for inputting/outputting an electrical signal through a probe tip, which directly makes contact with the conductive bump. The probe card analyzes the electrical signal to detect the defects of the semiconductor chip on which the conductive bump is formed.
A conductive bump may be formed using an electroplating solution and an electroplating process. The electroplating solution may include a compound having a cyano group or a compound without a cyano group. Lately, an electroplating solution including a compound without a cyano group, such as sodium gold sulfite (Na3Au(SO3)2), has been more widely used than an electroplating solution including a compound having a cyano group, such as potassium gold cyanide (KAu(CN)2). As a result, a toxic gas such as hydrogen cyanide (HCN) is not generated during a subsequent process. Further, the conductive bump has a denser structure.
However, when the conductive bump is formed using a compound without the cyano group, impurities may remain on the conductive bump. Such impurities may cause a process error during an EDS process. More particularly, when an under-bump metallurgy (UBM) layer exposed by the conductive bump is etched, impurities may be generated and the generated impurities may attach to a probe tip and cause an error in the analysis of an electrical signal. The impurities may include metal impurities such as aluminum (Al) from a pad or titanium (Ti) from the UBM layer, polyimide or silicon oxynitride (SiON) from a passivation layer, or oxide impurities such as aluminum oxide or titanium oxide. As a result of such impurities, although a semiconductor chip may be appropriately performed, the probe station may output inappropriate results indicating an electrical short or an electrical open circuit in the semiconductor chip.
In view of the foregoing, a cleaning process may be performed to remove the impurities from tip(s) of a probe card before and/or after an EDS process. However, cleaning processes may be abrasive and may damage the probe tip. Thus, productivity may be reduced. Further, such cleaning processes may not sufficiently remove the impurities from a probe tip. Thus, a method(s) capable of preventing generation of the impurities is desired.